1. Technical Field
The present invention relates generally to a semiconductor integrated circuit, and more particularly, to a semiconductor apparatus.
2. Related Art
A semiconductor apparatus receives a clock and operates in synchronization with the received clock. In order for the semiconductor apparatus to output a signal synchronized with the received clock, the semiconductor apparatus internally generates a delay-locked clock (DLL).
Referring to FIG. 1, a conventional semiconductor apparatus includes a DLL clock generation unit 10, an output enable signal generation unit 20, and a power-down control unit 30.
The DLL clock generation unit 10 receives a clock CLK and generates a DLL clock CLK_dll, and is activated or deactivated in response to a reset signal Reset.
The DLL clock generation unit 10 includes a buffer 11, a delay line 12, a replica 13, a phase comparing section 14, and a delay control section 15.
The buffer 11 buffers the clock CLK when activated and generates a buffering clock CLK_bf when a buffer enable signal Buf_en is enabled, and is deactivated and locks the buffering clock CLK_bf to a specified level when the buffer enable signal Buf_en is disabled.
The delay line 12 determines a delay time in response to delay control signals ctrl_dl<0:4>, delays the buffering clock CLK_bf by the determined delay time, and outputs the DLL clock CLK_dll.
The replica 13 delays the DLL clock CLK_dll and outputs a feedback clock CLK_fb. The delay time of the replica 13 is set as is the internal delay time of the semiconductor apparatus as modeled.
The phase comparing section 14 compares the phases of the feedback clock CLK_fb and the buffering clock CLK_bf, and generates a comparison signal com_s.
The delay control section 15 generates the delay control signals ctrl_dl<0:4> in response to the comparison signal com_s. For example, the delay control section 15 outputs the delay control signals ctrl_dl<0:4> of (0, 0, 1, 0, 0) as an initial value, outputs the delay control signals ctrl_dl<0:4> of (0, 1, 0, 0, 0) or (1, 0, 0, 0, 0) when the comparison signal com_s is enabled, and outputs the delay control signals ctrl_dl<0:4> of (0, 0, 0, 1, 0) or (0, 0, 0, 0, 1) when the comparison signal com_s is disabled.
The output enable signal generation unit 20 receives a read command signal RD_cmd, outputs an output enable signal OE_signal when a preset cycle of the DLL clock CLK_dll elapses thereafter, and is activated or deactivated in response to the reset signal Reset.
The power-down control unit 30 generates the buffer enable signal Buf_en and the reset signal Reset in response to a clock enable signal CKE and a self-refresh signal Sref. For example, the power-down control unit 30 disables the buffer enable signal Buf_en when the clock enable signal CKE is disabled. Also, the power-down control unit 30 enables the reset signal Reset when the clock enable signal CKE is disabled and the self-refresh signal Sref is enabled.
In a power-down mode of the conventional semiconductor apparatus when a state in which the clock enable signal CKE is disabled, the buffer 11 of the DLL clock generation unit 10 is deactivated. Accordingly, the delay line 12 of the DLL clock generation unit 10 maintains a delay time before the buffer 11 is deactivated.
When entering a self-refresh mode from the power-down mode, both the DLL clock generation unit 10 and the output enable signal generation unit 20 are deactivated.
If the power-down mode accompanied with these operations frequently occurs, the DLL clock generation unit 10 and the output enable signal generation unit 20, which operate by receiving the output signal of the DLL clock generation unit 10, are repeatedly activated and deactivated, by which the likelihood of a misoperation increases.